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Shaping Silicon, Powering Intelligence. This prototype phase company is founded and owned by Bibin Nandhyattu Biji.
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Yarok14
Embedded Software Test Engineer
June 13, 2026 – Present
l2_cache_RTL_FV_TB_UVM_DFT
March 18, 2026 – Present
Parameterized 256KB L2 Cache Controller — SystemVerilog RTL, MESI Coherency, AXI4/ACE, UVM-1.2 Testbench, JasperGold FPV, DFT Scan/BIST, Synopsys DC Synthesis, Cadence Innovus P&R
View ProjectGPU-SerDes-PCIe-NVLink-RTL-UVM-Project
February 3, 2026 – Present
Behavioral-to-architectural RTL model of a GPU-style SerDes subsystem
View Project16-bit-Pipelined-RISC-Processor-RTL-to-GDSII
January 31, 2026 – Present
16-bit Pipelined RISC Processor (RTL → GDSII): Executed full DC-ICC2-PrimeTime-Calibre flow; achieved WNS +0.03 ns, TNS 0; completed CTS, MCMM STA, IR/EM, and DRC/LVS sign-off using fully automated TCL scripts (3-nm production-grade methodology).
View ProjectFormal-Verification-With-VC-Formal-Tutorials-and-Examples
December 25, 2025 – Present
This repository is a structured learning and reference resource for Formal Verification using Synopsys VC Formal. It covers core concepts, real applications, setup guides, reports, and project artifacts, suitable for students, researchers, and industry engineers
View ProjectNetwork-on-Chip-NoC-Verilog-RTL-Implementation
December 24, 2025 – Present
Verilog RTL implementation of a packet-switched Network-on-Chip with input buffering, virtual channel allocation, switch allocation, and crossbar-based routing.
View ProjectLLM-Project-QLoRA-Finetuning-Quantization-FastAPI-Deployment-vLLM-Docker-
December 5, 2025 – December 6, 2025
End-to-end LLM pipeline: QLoRA finetuning (1B–7B), LoRA merge, GPTQ/AWQ quantization, FastAPI + vLLM inference server, GPU-ready Docker deployment, VRAM calculator, and a clean, production-grade modular repo structure.
View ProjectNo-GPS_Autonomous-Drone-System
November 23, 2025 – November 23, 2025
PX4 + ROS2 + Visual SLAM + VIO + Obstacle Avoidance + Autonomous Return Home A fully autonomous drone capable of navigating, mapping, avoiding obstacles, detecting targets, and returning to its launch position without GPS. Designed for research-grade missions, ISRO-style No-GPS challenges, DARPA-style underground navigation, and autonomous flight.
View Projectfront-end-ASIC-design-Local-Device-LMM-tool-using-RAG
November 22, 2025 – Present
Automated Front-End VLSI Design tool. Uses an LLM-RAG pipeline to transform high-level design specifications into PPA-optimized, synthesizable RTL IP blocks (Verilog/VHDL). Features an iterative verification loop for bug correction and quality assurance.
View ProjectAMBA-APB-Protocol
December 22, 2024 – June 12, 2025
AMBA-APB-Protocol — GitHub repository
View ProjectCultural Fit Analysis
The candidate's project portfolio is heavily focused on hardware design, verification, and VLSI, which aligns well with the technical demands of an Embedded Software Test Engineer role, especially in a hardware-centric environment. The projects demonstrate a strong initiative and self-driven learning, which are positive indicators for cultural fit in a technically demanding role. However, the current experience level is listed as 0, and the only listed experience is a future role, which makes it difficult to assess actual professional experience and cultural integration in a team setting. The projects are primarily personal, which, while showcasing technical prowess, doesn't provide insight into collaborative work or corporate culture fit.
Soft Skills & Operational Fit
The candidate's project descriptions indicate a strong problem-solving aptitude and a drive for complex technical challenges. The diversity of projects suggests adaptability and a willingness to learn new domains. However, without psychometric test results or interview data, it is difficult to assess specific soft skills like teamwork, stress handling, or communication clarity in a collaborative environment.