vijayan

Embedded Software Test Engineer

https://talent.gravityer.com/vijayan

https://www.chipwaretechnologies.com/

Key Strengths

Extensive experience with Verilog, Tcl, and C++ for hardware description and automation, highly relevant for embedded software testing.
Demonstrated proficiency in RTL-to-GDSII flows (OpenROAD, OpenLane), indicating a strong understanding of the hardware development lifecycle.
Practical experience with Makefiles and Dockerfiles, suggesting capability in build automation and environment setup.
Involvement in multiple personal projects related to digital signal processing (DSP), AES encryption, and RISC-V based systems, showcasing a deep interest and hands-on experience in embedded systems.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio is heavily focused on open-source hardware design and automation, which aligns well with a collaborative, technically driven culture. However, the projects are predominantly personal and academic in nature, with limited information on team collaboration or broader industry application. The single listed professional experience is current and recent, providing insufficient historical context for cultural fit assessment.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.

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Projects

opensta_power_example

February 14, 2023 – April 13, 2023

opensta_power_example — GitHub repository

View Project

DSP_DAC_GFMPW0

November 30, 2022 – December 3, 2022

DSP Processor for GF180 MPW shuttle

View Project

AES128_GFMPW0

November 25, 2022 – December 3, 2022

AES128 design submission for GF180 MPW0 Shuttle

View Project

graphics_controller_resubmit

November 25, 2022 – November 30, 2022

MPW7 resubmission

View Project

graphics_controller

August 31, 2022 – November 29, 2022

graphics_controller — GitHub repository

View Project

RISCV_Based_BMS

August 1, 2022 – August 1, 2022

RISCV_Based_BMS — GitHub repository

View Project

OpenLane-MPW-CI

February 16, 2022 – October 5, 2024

OpenLane-MPW-CI — GitHub repository

View Project

OpenROAD-flow-scripts

July 28, 2020 – Present

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

View Project

OpenLane

July 20, 2020 – Present

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

View Project

OpenROAD

October 28, 2019 – Present

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

View Project

Key Strengths

Extensive experience with Verilog, Tcl, and C++ for hardware description and automation, highly relevant for embedded software testing.
Demonstrated proficiency in RTL-to-GDSII flows (OpenROAD, OpenLane), indicating a strong understanding of the hardware development lifecycle.
Practical experience with Makefiles and Dockerfiles, suggesting capability in build automation and environment setup.
Involvement in multiple personal projects related to digital signal processing (DSP), AES encryption, and RISC-V based systems, showcasing a deep interest and hands-on experience in embedded systems.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.

vijayan

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Experience

Projects

Key Strengths

Cultural & Operational Fit