shreekanth

FPGA Developer

https://talent.gravityer.com/shreekanth-1

Electronics and communication Engineer👨‍🎓

Bengaluru, Karnataka, India

Key Strengths

Demonstrated experience with Verilog HDL through personal projects like 'verilog-spi-master-controller' and 'uart-verilog-transceiver', directly aligning with an FPGA Developer role.
Practical application of FSM design and FIFO buffering in Verilog, indicating foundational FPGA design skills.
Experience with verification using GTKWave and CI/CD with GitHub Actions for hardware description languages.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate shows initiative through numerous personal projects across different domains (FPGA, Embedded C++, Python networking, desktop applications). This indicates a proactive learning attitude and a broad interest in technology. The focus on Verilog projects directly aligns with the target role, suggesting a strong interest in the domain.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are clear but do not provide insight into collaboration, problem-solving approaches, or communication style.

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Evaluating your skill match against the job requirements…

Assessing your cultural and operational fit

Projects

verilog-spi-master-controller

May 8, 2026 – Present

FSM-based SPI Master Controller in Verilog HDL with FIFO buffering, configurable SPI modes, GTKWave verification, and GitHub Actions CI.

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uart-verilog-transceiver

May 4, 2026 – Present

uart-verilog-transceiver — GitHub repository

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line-fault-detection-esp32

April 24, 2026 – Present

ESP32-based IoT Line Fault Detection System with GPS & Blynk

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stm32-learning

April 23, 2026 – Present

stm32-learning — GitHub repository

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network-monitoring

April 22, 2026 – Present

Python CLI network monitoring tool for tracking device availability, detecting status changes, and logging events.

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subnet-calculator

April 22, 2026 – Present

Python CLI subnet calculator with CIDR parsing, subnet splitting, wildcard mask generation, and binary conversion.

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network-scanner

April 22, 2026 – Present

Multi-threaded Python CLI network scanner for host discovery, latency measurement, and TCP port scanning with configurable timeout and threading.

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embedx

March 29, 2026 – Present

Fast, modern CLI for embedded development — build, upload, and manage projects with ease.

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BSMS

March 25, 2026 – Present

Battery Sales Management System (BSMS) – A Python desktop application for managing inventory, sales, customers, and role-based access with real-world workflow design.

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Caesar-Cipher-CLI-Tool

November 25, 2025 – November 25, 2025

this is an activity which i did for collage (computer Network Security) under Encryption and Decryption method

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Key Strengths

Demonstrated experience with Verilog HDL through personal projects like 'verilog-spi-master-controller' and 'uart-verilog-transceiver', directly aligning with an FPGA Developer role.
Practical application of FSM design and FIFO buffering in Verilog, indicating foundational FPGA design skills.
Experience with verification using GTKWave and CI/CD with GitHub Actions for hardware description languages.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

shreekanth

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit