Shashank Obla

FPGA Developer

https://talent.gravityer.com/shashank-obla

PhD Student in the ECE Department at Carnegie Mellon University

Carnegie Mellon University

Key Strengths

Extensive personal project experience in FPGA development, including VHDL, Verilog, and SystemVerilog.
Demonstrated experience with High-Level Synthesis (HLS) and Network-on-Chip (NoC) design.
Proficiency in C++ and scripting languages like Python and Shell, useful for tooling and automation in FPGA workflows.
Experience with RISC processor design and pipelining, indicating a strong understanding of digital design principles.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong focus on hardware description languages and digital design, aligning well with an FPGA Developer role. The diversity of projects, from encryption to processor design and NoC, indicates a broad interest within the hardware domain. However, the lack of team-based projects or professional experience (beyond a future role) makes it difficult to fully assess cultural fit.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.

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Assessing your cultural and operational fit

Projects

ReCONNECT

August 24, 2023 – Present

ReCONNECT: FPGA Optimized RTL-Native Parameterized Network-on-Chip

View Project

18-645_Project

October 21, 2022 – December 15, 2022

18-645_Project — GitHub repository

View Project

file_encryption_aes

July 11, 2019 – July 15, 2019

AES Encryption and Decryption using C++

View Project

Minesweeper

December 28, 2018 – December 28, 2018

Minesweeper — GitHub repository

View Project

Tutorials

August 11, 2018 – October 4, 2018

Tutorials — GitHub repository

View Project

Pipelined_IITB-RISC

May 5, 2017 – November 23, 2018

Pipelined_IITB-RISC — GitHub repository

View Project

PasswordManager

May 4, 2017 – May 4, 2017

Password Manager to store all your passwords using a master password

View Project

EE739-Advanced-Processor-Design

March 5, 2017 – May 4, 2017

EE739-Advanced-Processor-Design — GitHub repository

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HighLevelSynthesis

December 5, 2016 – December 5, 2016

HighLevelSynthesis — GitHub repository

View Project

DAQ_GUI

September 28, 2015 – December 14, 2015

GUI for Data Acquisition for IIT Bombay Racing

View Project

Key Strengths

Extensive personal project experience in FPGA development, including VHDL, Verilog, and SystemVerilog.
Demonstrated experience with High-Level Synthesis (HLS) and Network-on-Chip (NoC) design.
Proficiency in C++ and scripting languages like Python and Shell, useful for tooling and automation in FPGA workflows.
Experience with RISC processor design and pipelining, indicating a strong understanding of digital design principles.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.

Shashank Obla

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Experience

Projects

Key Strengths

Cultural & Operational Fit