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IIT(BHU) Varanasi
Data Scientist
June 18, 2026 – Present
riscv-ms-soc
May 29, 2022 – May 31, 2022
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
View Projecthdlbits-verilog-funda
March 7, 2022 – July 28, 2022
hdlbits-verilog-funda — GitHub repository
View ProjectMorse-Decoder-Schematic
January 29, 2022 – May 25, 2022
Morse Code Decoder using Digital Logic
View Projectpowerline-fault-detection
January 21, 2022 – January 21, 2022
powerline-fault-detection — GitHub repository
View Projectriscv-tlv-core
December 13, 2021 – June 16, 2022
A simple implementation of a RISC-V core (RV32I) written in TL Verilog.
View ProjectMaskRCNN_tryout
September 17, 2020 – May 25, 2022
Instance Segmentation using Mask RCNN(with pretrained weights of COCO dataset)
View ProjectHand-Imitation
June 6, 2020 – October 9, 2020
RL based learning for a robotic arm to imitate a given hand in a image feed
View ProjectCultural Fit Analysis
The candidate's projects show a strong inclination towards hardware design and embedded systems, with some exposure to machine learning. While the target role is 'Data Scientist', the majority of projects lean towards hardware and low-level programming. This indicates a potential mismatch in core interests and the target role's typical responsibilities, though the ML projects show some alignment. The candidate's experience level is 0, and the listed 'Data Scientist' role is current but starts in the future (2026), suggesting it might be an upcoming academic or research position rather than professional experience.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. The psychometric test score is 0, providing no insights.