renonesopocaj

FPGA Developer

https://talent.gravityer.com/renonesopocaj

MSc Computer Science @ EPFL | BSc Engineering of Computing Systems @ PoliMi

Member since June 28, 2026

Key Strengths

Demonstrated experience with VHDL through personal projects ('VHDL_project', 'VHDL-filter'), directly aligning with an FPGA Developer role.
Proficiency in C++ and Python, which are valuable for scripting, simulation, and potentially high-level synthesis in FPGA development.
Experience with algorithms and data structures ('AlgoDataStruct-project'), crucial for efficient hardware design.
Exposure to optimization and algorithmic applications ('BanditDL', '3d-queens-mcmc'), indicating a strong analytical foundation.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong inclination towards personal learning and exploration across various technical domains, including VHDL, algorithms, and machine learning. This self-driven approach suggests a good cultural fit for environments that value continuous learning and initiative. The diversity of projects indicates adaptability and a broad technical curiosity.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback are available.

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Projects

BanditDL

April 27, 2026 – Present

Project for Optimization for ML class at EPFL

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3d-queens-mcmc

April 7, 2026 – Present

MCMC (Markov Chain Monte Carlo) solver of the 3d $N^2$ queens problem via Metropolis Hastings and a clever state space optimization for the "Markov Chains and Algorithmic Applications" project @ EPFL, A.Y. 2025-2026. Team: Chengheng Li Chen, Francisco Badia Laguillo, Jacopo Senoner.

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gibbons

December 12, 2025 – Present

gibbons — GitHub repository

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VHDL-filter

September 29, 2025 – Present

VHDL-filter — GitHub repository

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spo2t

August 10, 2025 – August 10, 2025

OSA (obstructive sleep apnea) detection via MAX30102 connected to a Nicla Sense ME running the inference of the MLP.

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VHDL_project

August 6, 2025 – Present

VHDL_project — GitHub repository

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ing-sw-2025-tedesco-tenti-zanelli-senoner

March 2, 2025 – Present

Final project of the "Software engineering" exam, Politecnico di Milano, A.Y. 2024-2025

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recaptcha-solver-selenium

December 6, 2024 – December 20, 2024

A recaptcha v2 solver in python using selenium (or seleniumwire) and undetectable chromedriver

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quadric-canonicalizer

December 4, 2024 – Present

A program that brings a quadric surface in canonical form and renders the transformation.

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AlgoDataStruct-project

November 29, 2024 – April 2, 2025

Final project of the "Algorithms and Data Structures" course @ PoliMi, A.Y. 23-24, Final Mark 30L/30. Professor: Davide Martinenghi.

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Key Strengths

Demonstrated experience with VHDL through personal projects ('VHDL_project', 'VHDL-filter'), directly aligning with an FPGA Developer role.
Proficiency in C++ and Python, which are valuable for scripting, simulation, and potentially high-level synthesis in FPGA development.
Experience with algorithms and data structures ('AlgoDataStruct-project'), crucial for efficient hardware design.
Exposure to optimization and algorithmic applications ('BanditDL', '3d-queens-mcmc'), indicating a strong analytical foundation.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback are available.

renonesopocaj

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit