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Asic Soc Silicon Verification Engineer with 1+ years in IP and System-on-Chip verification.
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Verification Engineer with 1 year of experience in IP and System on Chip-level verification. Strong understanding of System Verilog, Universal Verification Methodology, and Verilog, with hands-on experience in testbench development, assertion-based verification, and functional/code coverage analysis. Skilled in verifying high-speed bus protocols such as I2C and AXI ensuring compliance and performance. Proficient in using industry-standard simulators like Synopsys Vnc and waveform debugging tools for ASIC and SoC verification.
Sri indu institute of engineering and technology
B. Tech · Electronics and Communication Engineering
January 1, 2020 – January 1, 2024
Krishnaveni Co-op Junior college Khammam
Intermediate Education
January 1, 2018 – January 1, 2020
Mother Theresas Vidyalayam Sathupally
SSC
January 1, 2018 – January 1, 2018
Sumedha Institute of Technology
Design Verification Engineer Trainee
February 1, 2025 – Present
India
Design Verification of Synchronous FiFo using System Verilog
June 1, 2026 – Present
Verified a synthesizable Synchronous First-In, First-Out (FIFO) RTL design using a System Verilog Testbench that adhered to a custom, module-level verification environment. Developed key verification components in System Verilog, including: Transactor/Driver: To generate and drive randomized data and control signals (write enable, read enable) into the FIFO's Write interface. Monitor: To non-intrusively sample data and protocol signals on both the Write and Read interfaces. Designed a Golden Reference Model (Checker/Scoreboard) in SystemVerilog to replicate ideal FIFO behavior and compare the actual output data with the expected data sequence, ensuring data integrity. Implemented complex, randomized test scenarios using System Verilog's constrained random methodology (e.g., rand, constraint blocks) to rigorously test corner cases such as: Simultaneous read and write operations near full/empty boundaries, Overflow and Underflow conditions, Burst transfers (rapid successive reads or writes). Utilized System Verilog Assertions (SVA) to formally verify critical design properties, such as ensuring the full flag is asserted when the last word is written and the empty flag is asserted when the last word is read. Analysed code coverage (Line, Toggle, FSM coverage) metrics to ensure all RTL code paths were exercised, and used the simulator and waveform viewer for efficient debugging and root-cause analysis.
Design and Verification of I2C Protocol using IP Verification
June 1, 2026 – Present
Verified an I²C Bus Controller IP (Master/Slave functionality) for compliance with the I²C Protocol Specification, focusing on key features like 7-bit addressing, clock stretching, and bus arbitration. Developed a Reusable Verification Environment in System Verilog, including Driver (to generate transactions) and Monitor (to capture bus activity). Implemented a Scoreboard (Golden Reference Model) to compare captured bus transactions with expected behaviour, thereby ensuring data integrity and protocol adherence. Designed and executed constrained-random test scenarios to rigorously test corner cases, including bus arbitration contention, stop/start conditions, and varying data transfer rates. Applied System Verilog Assertions (SVA) to formally verify protocol rules and timing constraints, such as validating Start/Stop conditions and Acknowledge (ACK/NACK) cycle. Achieved verification closure by tracking functional coverage of critical I²C states and analyzing code coverage using industry-standard simulation tools.
Design Verification Engineer
Sumedha Institute of Technology
June 1, 2026 – Present
Cultural Fit Analysis
The candidate's academic projects demonstrate a focused interest in ASIC/SoC verification, directly aligning with the target role. The projects showcase a methodical approach to verification, including testbench development, coverage analysis, and assertion-based verification, which suggests a good fit for a detail-oriented and quality-focused engineering culture. The limited professional experience (internship starting in the future) means there is less data to assess broader cultural fit aspects like collaboration in a diverse team or navigating corporate dynamics.
Soft Skills & Operational Fit
The candidate lists communication, teamwork, adaptability, problem-solving, and decision-making as soft skills. The project descriptions indicate an ability to work through complex technical problems independently, which aligns with problem-solving and decision-making. The academic nature of projects and limited professional experience means direct evidence of teamwork and adaptability in a corporate operational setting is not yet available.