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M.Tech VLSI Design | Analog/RF IC Design | LNA Design (2.4 GHz & UWB) | Cadence Virtuoso | RTL-to-GDSII Flow | Verilog | Synopsys VCS | Design Compiler | ICC2
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Student
FPGA Developer
June 19, 2026 – Present
Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier
April 14, 2026 – Present
Performance-Balanced-Noise-Canceling-Low-Noise-Amplifier — GitHub repository
View ProjectDesign-and-analysis-of-Low-power-hybrid-full-adder-for-array-multiplier-in-90nm-technology
October 21, 2025 – October 21, 2025
Design-and-analysis-of-Low-power-hybrid-full-adder-for-array-multiplier-in-90nm-technology — GitHub repository
View ProjectUltra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application
October 21, 2025 – October 21, 2025
Ultra-Lightweight-RISC-V-Architecture-for-Anomaly-Detection-in-Healthcare-Application — GitHub repository
View ProjectCultural Fit Analysis
The candidate's projects show a strong alignment with the target role of FPGA Developer, indicating a passion for the domain. The diversity of projects, including noise-canceling LNA and RISC-V architecture, suggests a broad interest within VLSI/FPGA. However, the experience level is listed as 0, and the current role is 'Student', which might indicate a need for mentorship and structured guidance in a professional setting.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.