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Logic Design Manager
Senior SoC Design & Integration Manager with 20+ years of experience leading frontend and backend design teams at Intel and Marvell. Proven expertise in leading RTL teams in IP and SOC level, RTL2GDS implementation, low-power methodologies, and managing global engineering teams delivering complex semiconductor projects. Strengths: Excellent progression from individual contributor to senior management Strong technical depth across both frontend and backend design Leadership experience with global teams Hands on experience on all tools and flows I lead. Relevant experience at top-tier companies (Intel, Marvell) Work Experience: 2021 - present - IPU SNIC FC & IP Logic Design Manager at Intel • Leading the FC design, integration and methodology work. • Lead cross-functional team of 7 FE design engineers, delivering 3 major SoC projects on schedule while implementing new methodologies that reduced design cycles by 20%. 2018 - 2021- IP Logic Design Manager at Intel • Leading Thunderbolt (USB4) IP logic design team. • Working closely with global integration teams. 2017 - 2018 - Hardware Backend Leader at Intel • Leading team of backend engineers through RTL2GDS on macro level and FCT on SOC in 28nm process. 2015 - 2017 - Marvell iSOC Group Senior Backend Manager • Leading team of backend engineers through RTL2GDS implementation on blocks, FCT. • Managed project backend resources in China. 2014 – 2015 - Marvell COT-PD -- Cellular Group Senior Backend Manager • Managed the PD resources under a global department using the group flows and tools. • Implemented the FC integration in Israel, US, China teams. • Developed new methodologies and shared with global teams. • Supporting BE phases using low power techniques on high freq designs. 2006 - 2014 - Marvell CHG - Backend Manager • Responsible for floorplan, P&R, synthesis and STA on blocks and
The College of Management Academic Studies
Bachelor of Science (BSc), Computer Science
January 1, 2009 – January 1, 2012
Intel Corporation
SoC FE integration manager
June 1, 2021 – Present
Israel
Broadcom Inc.
ASIC Design Engineer
March 1, 2021 – June 1, 2021
Tel Aviv District, Israel
Intel Corporation
Hardware Logic Design Leader
December 1, 2017 – March 1, 2021
Israel
Intel Corporation
Harware Backend Leader
April 1, 2017 – December 1, 2017
Israel
Marvell
Senior Backend Manager
November 1, 2006 – December 1, 2017
Isra
Intel
Physical Design team manager
June 1, 2005 – November 1, 2006
Intel (DSPC)
Physical Design CHG PTK
December 1, 2000 – November 1, 2006
Cultural Fit Analysis
The candidate has a long and consistent career path within large semiconductor corporations, indicating a fit for structured, large-scale engineering environments. The target role of 'FPGA Developer' is a direct match for the candidate's background in hardware design and SoC integration, suggesting a strong cultural and technical alignment with roles requiring deep hardware expertise. However, the lack of project diversity outside of large corporate roles might indicate a specific type of cultural fit.
Soft Skills & Operational Fit
The candidate's extensive experience in leadership roles (manager, leader) suggests strong operational fit and soft skills related to team management, project execution, and potentially cross-functional collaboration. However, without specific psychometric test results or interview data, a detailed assessment of stress handling, work attitude, and team collaboration is not possible.