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Lead Engineer
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
Experienced Design Verification Engineer with a strong background in system design and verification, specializing in SystemVerilog, UVM, and tools like VCS Verdi and Model Sim. Proficient in protocols such as I2C, AXI, and APB. My work spans top-tier firms like Synopsys and 7 Rays, focusing on developing innovative solutions for complex semiconductor challenges. Eager to connect with like-minded professionals and explore opportunities that leverage my expertise to advance cutting-edge technologies.
CDAC, Noida
Master’s Degree, VLSI
January 1, 2014 – January 1, 2016
lord krishna college of engineering
Engineer’s Degree, Electronics and Communications Engineering
January 1, 2009 – January 1, 2013
7Rays Semiconductors
Lead Engineer
April 1, 2026 – Present
On-site
7Rays Semiconductors
Senior Verification Engineer
December 1, 2023 – May 1, 2026
On-site
VerifWorks
Design Verification Engineer
September 1, 2021 – January 1, 2023
Bengaluru, Karnataka, India · Remote
Career Break
Caregiving
November 1, 2018 – August 1, 2021
Synopsys Inc
Post Graduate Engineer
July 1, 2016 – October 1, 2018
New Delhi Area, India · On-site
Cultural Fit Analysis
The candidate's experience is highly specialized in Design Verification, which aligns with the technical demands of an FPGA Developer role. However, the lack of diverse project experience or contributions outside of verification, and the absence of explicit FPGA development experience, suggests a potential gap in direct cultural fit for a pure FPGA development role without further validation.
Soft Skills & Operational Fit
The candidate's career break for caregiving demonstrates empathy, responsibility, and problem-solving skills. However, without specific project details or team collaboration examples, it is difficult to fully assess operational fit beyond individual technical contributions.