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Sr. SoC Physical Design Engineer (4/2019 -- present)
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Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
Executive and passionate Silicon Valley professional in ASIC physical design leader with expertise in all facets of high speed, high gate density and high pin count chip design, complete ASIC physical design flow from RTL to tape out, RP and customized macro design. TSMC N16, N10 and beyond advanced tech nodes within high-profile corporations. Skilled in collaborating with all members of the organization to achieve business and financial objectives. Instrumental in streamlining and improving processes, enhancing productivity, and implementing technology solutions. Technical Proficiency in Synopsys DCG, ICC, ICC2, ICV, StarRc and PT, Cadence synthesis and ATPG.
San José State University
Master's degree, Electrical and Electronics Engineering
N/A – Present
Meta (LTTS)
Sr. Physical Design Engineer
August 1, 2022 – July 1, 2023
Menlo Park, California, United States · Remote
Samsung Electronics America
Sr. SoC Physical Design Engineer (Xorint)
April 1, 2019 – May 1, 2021
San Jose, CA
Intel Corporation (Esencial Tech)
Sr. ASIC Physical Design Engineer
October 1, 2017 – October 1, 2018
Santa Clara, CA
Google (Synapse-Da)
Sr. Physical Design Contractor
March 1, 2017 – September 1, 2017
1220 N. Mathilda Ave., Sunnyvale, CA
Huawei Technologies
ASIC Backend Design lead
January 1, 2010 – February 1, 2017
Santa Clara, CA
LT Design & Consulting
Sr Hardware Contractor
August 1, 2009 – July 1, 2010
Force10 Networks
Principle Technical Staff (ASIC Physical Design)
January 1, 2000 – January 1, 2009
San Jose CA
ELAN Group, Lucent Technologies
Member of Technical Staff
January 1, 1998 – January 1, 2000
Milpitas, CA
Cultural Fit Analysis
The candidate has a long and varied career in ASIC/SoC physical design, working with multiple large technology companies. While the target role is 'FPGA Developer', the candidate's background is heavily focused on ASIC physical design. This represents a significant domain shift. While there are foundational hardware design principles that overlap, the specific tools, methodologies, and design flows for FPGA development (e.g., Verilog/VHDL for RTL, synthesis for FPGAs, place & route for FPGAs, specific FPGA vendor tools like Xilinx Vivado or Intel Quartus) are not explicitly mentioned in the resume. This indicates a potential gap in direct cultural fit for an FPGA-centric team without significant upskilling or a broader interpretation of the 'FPGA Developer' role to include general hardware design expertise.
Soft Skills & Operational Fit
The candidate's extensive experience across various major semiconductor companies (Meta, Samsung, Intel, Google, Huawei) suggests adaptability and the ability to integrate into diverse operational environments. The detailed descriptions of complex physical design tasks imply strong problem-solving skills and attention to detail. The role as a 'lead' at Huawei indicates leadership and potentially mentoring capabilities.