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R V College of Engineering
FPGA Developer
June 25, 2026 – Present
FPGA_Workshop_VSD
December 14, 2022 – December 23, 2022
This Repo is a part of a 5-Day Workshop conducted by VLSI System Design (VSD) and the contents are divided Day wise for better understanding.
View ProjectBraun-Multiplier
December 4, 2022 – December 8, 2022
Braun-Multiplier — GitHub repository
View ProjectFFT
November 28, 2022 – December 25, 2022
This repo is a small self project for improving technical skills in digital designing by designing a 16-bit FFT...... Still a long way to go
View ProjectJohnsonCounter_LP
October 8, 2022 – January 8, 2023
JohnsonCounter_LP — GitHub repository
View ProjectVerilog_Practice
September 14, 2022 – October 7, 2022
Verilog_Practice — GitHub repository
View ProjectCultural Fit Analysis
The candidate demonstrates a strong interest in FPGA development through a consistent portfolio of personal projects. The projects cover various aspects of digital design, suggesting a breadth of interest within the FPGA domain. The current role as an 'FPGA Developer' at R V College of Engineering aligns directly with the target role. The engagement in a VSD workshop indicates a proactive approach to learning and community involvement, which generally contributes positively to cultural fit. However, the lack of team-based projects or detailed descriptions of collaboration makes it difficult to fully assess team collaboration aspects.
Soft Skills & Operational Fit
The candidate's project descriptions are brief, making it difficult to assess communication clarity or depth of understanding beyond technical keywords. The psychometric and English test scores are 0, indicating no data for these assessments, thus no assessment of soft skills or operational fit can be made from the provided data.