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Principal Engineer at D2S, Inc.
I have more than 30 years of experience leading and developing EDA and IP products combining a deep knowledge of hardware and software and with a passion for delivering a high quality product. I'm applying deep learning to problems in electronics manufacturing Specialties: EDA tools and methodologies, especially high-level synthesis, SOC modeling and EDA databases. Software for semiconductor manufacturing. System Architecture, especially interconnect and DRAM performance. Deep Learning. Languages: Python (including NumPy, Pandas and TensorFlow), MATLAB, C++, C, CUDA, Verilog, SystemC, & Skill.
Carnegie Mellon University
MS, Electrical Engineering
January 1, 1980 – January 1, 1981
University of Nebraska-Lincoln
BS, Computer Science
August 1, 1976 – December 1, 1979
D2S, Inc.
Principal Engineer
January 1, 2023 – Present
D2S, Inc.
VP of Engineering, TrueMask(R) products
February 1, 2020 – January 1, 2023
Center for Deep Learning in Electronics Manufacturing (CDLe)
Principal
October 1, 2018 – January 1, 2020
San Jose
D2S, Inc.
Principal, Deep Learning
March 1, 2018 – September 1, 2018
San Jose, CA
Self-employed
Exploring new areas
May 1, 2017 – February 1, 2018
San Francisco Bay Area
Cadence Design Systems
Fellow - IPG (CTO/Systems & Software)
January 1, 2016 – April 1, 2017
Cadence Design Systems
Fellow - IPG VIP
December 1, 2014 – December 1, 2015
Cadence Design Systems
Fellow - System Level Design (SLD)
April 1, 2010 – November 1, 2014
Cadence Design Systems
VP R&D - C-to-Silicon
May 1, 2005 – April 1, 2010
Sonics, Inc.
VP of Engineering
March 1, 2001 – November 1, 2004
Sonics, Inc.
Director of Software Development
November 1, 1998 – March 1, 2001
Cadence
Fellow
January 1, 1995 – January 1, 1998
Cadence
Chief Arhitect
January 1, 1995 – January 1, 1998
Cadence
Framework Architect
January 1, 1991 – January 1, 1994
Cadence
Sr. Manager
January 1, 1988 – January 1, 1991
SDA Systems
Member of Technical Staff
October 1, 1984 – January 1, 1988
AT&T Bell Laboratories
Member of Technical Staff
February 1, 1980 – October 1, 1984
Cultural Fit Analysis
The candidate's career trajectory shows a strong fit for roles requiring innovation, technical leadership, and strategic direction within the semiconductor and EDA industries. Their experience with deep learning and exploring new areas demonstrates a willingness to adapt and learn, which is beneficial for dynamic environments. The target role of 'FPGA Developer' might be a slight mismatch given the candidate's primary experience in ASIC/SoC design and high-level synthesis, though the underlying digital design principles are transferable. The breadth of experience across different companies and roles suggests an ability to integrate into diverse technical cultures.
Soft Skills & Operational Fit
The candidate's extensive career progression into leadership and principal roles suggests strong leadership, strategic thinking, and problem-solving abilities. Their involvement in launching new products and leading development teams indicates operational effectiveness and a results-oriented approach. The long tenure at Cadence and Sonics implies loyalty and the ability to navigate complex organizational structures.