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Vice President of AI System Architecture @ Microsoft
With over 25 years of experience in processor architecture, efficient AI/ML, and AI systems, I lead Microsoft Azure AI System Architecture team. We architect the hardware-software foundation for Azure AI, translating AI model demands into scalable architectures for silicon, systems, and networks. My work focuses on performance-model driven co-design of AI accelerators, cloud-scale architectures, and low-latency networking to enable hyperscale AI performance. Passionate about advancing AI and machine learning, I bring deep technical expertise in AI workloads, accelerators, and parallelization. My role emphasizes collaboration with data science and GenAI teams, ensuring model and hardware co-design for innovation. Strategic vision, pragmatic technical leadership, and proven innovator: I have been granted over 100 patents.
Princeton University
MS, Electrical Engineering
January 1, 1995 – January 1, 1997
Rensselaer Polytechnic Institute
BS, Computer and Systems Engineering
January 1, 1991 – January 1, 1995
Microsoft
VP of AI Systems Architecture and Distinguished Engineer
December 1, 2025 – Present
TAU Ventures
Advisory Board Member
May 1, 2024 – Present
Microsoft
Vice President, AI Systems Architect
February 1, 2024 – December 1, 2025
Tenstorrent Inc.
Vice President, AI Hardware and Models
November 1, 2022 – February 1, 2024
Tenstorrent Inc.
Vice President, AI Models
January 1, 2022 – November 1, 2022
The Alan Turing Institute
Member Of The Board Of Advisors
July 1, 2019 – September 1, 2021
DataSig at Mathematical Institute, University of Oxford
ARM
Distinguished Engineer and Senior Director, Arm Machine Learning Research Lab
January 1, 2019 – October 1, 2021
ARM
Senior Director, Machine Learning Research
January 1, 2017 – January 1, 2019
ARM
Director, New Business Ventures
February 1, 2015 – January 1, 2017
Tilera Corporation
CTO
March 1, 2011 – February 1, 2015
Greater Boston Area · On-site
Tandberg (acquired by Cisco Systems)
Technical Lead
July 1, 2009 – March 1, 2011
Tilera
Lead Architect
July 1, 2005 – July 1, 2009
Greater Boston Area
Intel
Principal Engineer
January 1, 2001 – January 1, 2005
Greater Boston Area
Intel
Hardware Engineer
January 1, 1997 – January 1, 2001
Greater Boston Area
Cultural Fit Analysis
The candidate has a diverse background spanning large corporations (Microsoft, Intel, ARM) and startups (Tilera, Tenstorrent), indicating adaptability to different organizational cultures. Their involvement in founding research labs and driving new business ventures suggests an innovative and entrepreneurial mindset. The target role of 'FPGA Developer' is a significant shift from recent VP/CTO roles, which might indicate a desire for a more hands-on technical contribution, but also raises questions about their willingness to operate at a non-leadership level. While the candidate has direct FPGA experience from Tandberg, their recent roles have been at a much higher strategic and architectural level, potentially leading to a mismatch in day-to-day responsibilities for a pure developer role.
Soft Skills & Operational Fit
The candidate's extensive leadership roles (VP, CTO, Distinguished Engineer) indicate strong strategic thinking, cross-functional leadership, and the ability to build and manage high-performing technical teams. Their advisory board roles suggest strong communication and influence skills. The descriptions highlight a focus on translating complex technical demands into practical, scalable solutions, indicating a results-oriented approach.