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Former TSMC Director of Advanced Packaging Business Dev., scaling 3DFabric® / CoWoS® to $7B+ | Independent Director at Alchip | 40 years across TSMC, design service foundry, fabless, system house, IDM, & startups.
Jerry Tzou is currently serving as a Board Director at Alchip Technologies. He wrapped up his career at TSMC in 2025 as Director of Advanced Packaging Business Development. He spearheaded the strategic growth of TSMC’s 3DFabric® platform—CoWoS®, InFO, TSMC-SoIC®, TSMC-SoW™, and COUPE™ for Co-Packaged Optics (CPO) —tying it to TSMC’s advanced silicon innovations. Through synergistic collaboration with customers and ecosystem partners, this work enabled AI accelerators and next-gen packaging solutions for NVIDIA, AMD, Broadcom, Apple, hyperscalers, etc., growing advanced packaging revenue from <$0.5B to >$7B. Jerry’s 40-year semiconductor career included diverse roles at TSMC, VP of Product Operations at Global Unichip Corporation (GUC), a TSMC-affiliated design foundry, and advanced packaging work at Apple, National Semiconductor, Cirrus Logic, and select Silicon Valley startups. With a Master’s in Materials Science and Engineering from UC Berkeley, his expertise spans semiconductor packaging, operations, and business development.
University of California, Berkeley
M.S., Materials Science
January 1, 1981 – January 1, 1983
National Cheng Kung University
B.S.E., Metallurgy and Materials Engineering
January 1, 1975 – January 1, 1979
Alchip Technologies
Independent Board Director
May 1, 2025 – Present
Santa Clara County, California, United States
TSMC
Director, Advanced Packaging Business Development
June 1, 2020 – January 1, 2025
On-site
TSMC
Deputy Director, Advanced Packaging Business Development
November 1, 2010 – May 1, 2020
On-site
GUC
Vice President, Product Operations
February 1, 2009 – November 1, 2010
Hsinchu City, Taiwan · On-site
TSMC
Deputy Director
May 1, 1997 – January 1, 2009
On-site
ProLinx Labs Corporation
Manager, Process Development
August 1, 1996 – April 1, 1997
San Jose, California, United States
MicroUnity Systems Engineering, Inc.
Manager, Foundry Packaging and Assembly Operations
August 1, 1995 – July 1, 1996
Sunnyvale, California, United States · On-site
Cirrus Logic
Manager, Packaging and Assembly Operations
April 1, 1994 – August 1, 1995
Fremont, California, United States · On-site
Apple Computer
Staff Engineer, Worldwide PCB Mfg. & Ops.
November 1, 1988 – April 1, 1994
Cupertino, California, United States · On-site
National Semiconductor
Staff Packaging Engineer
November 1, 1984 – October 1, 1988
Santa Clara, California, United States · On-site
Cultural Fit Analysis
The candidate has a long and distinguished career primarily in semiconductor manufacturing and business development, with significant tenure at TSMC. While this demonstrates loyalty and deep industry knowledge, the target role of 'Quality Assurance Engineer' is a substantial shift from their executive and strategic roles. The project diversity is limited to their professional experience, and the breadth of skills listed (Product Development, Product Strategy, Manufacturing Engineering, Business Strategy, Strategic Planning) does not directly align with typical QA engineering skill sets (e.g., test automation, test methodologies, defect tracking, specific QA tools). This suggests a potential cultural mismatch for a hands-on QA role, though their deep industry knowledge could be valuable in a QA leadership or strategic quality role.
Soft Skills & Operational Fit
The candidate's extensive leadership roles (Director, VP, Manager) suggest strong leadership, strategic planning, and operational management skills. The descriptions indicate a collaborative approach (e.g., 'collaborated with leading industry players'). However, the target role of 'Quality Assurance Engineer' is a significant pivot from their executive and business development background, which may indicate a mismatch in operational fit for a hands-on QA role.