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Senior Chip Design Engineer
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
Ben-Gurion University of the Negev
Bachelor of Science (B.Sc.), Electrical and Electronics Engineering
January 1, 2008 – January 1, 2012
Senior ASIC design engineer
December 1, 2025 – Present
NeuroBlade
ASIC Design Engineer
October 1, 2021 – December 1, 2025
Marvell Israel Ltd.
ASIC IP Design and Verification Team Leader
November 1, 2019 – October 1, 2021
Marvell Israel Ltd.
Verification Engineer
November 1, 2018 – November 1, 2019
Marvell Israel Ltd.
Backend Team leader
August 1, 2017 – November 1, 2018
Marvell Israel Ltd.
Backend Engineer
July 1, 2013 – August 1, 2017
Freescale Semiconductor
Chip Design Engineer
August 1, 2012 – July 1, 2013
ELTA
System Engineering
March 1, 2007 – August 1, 2012
Cultural Fit Analysis
The candidate has a long tenure at Marvell Israel Ltd. and experience at Google and NeuroBlade, indicating stability and adaptability to different corporate environments. The progression from Backend Engineer to Team Leader and then to ASIC Design Engineer roles demonstrates a growth mindset. The target role of FPGA Developer aligns well with the candidate's core expertise in ASIC/FPGA design. However, the lack of diverse project descriptions outside of core ASIC/FPGA work limits a full assessment of cultural fit.
Soft Skills & Operational Fit
The candidate's experience as a team leader and in various design and verification roles suggests strong collaboration and problem-solving skills. The detailed descriptions of ASIC/FPGA uArch and RTL design indicate a methodical approach to complex technical challenges. However, without psychometric test results, a definitive assessment of stress handling or team collaboration is not possible.