Giovanni Rebecchi

FPGA Developer

https://talent.gravityer.com/giovanni-rebecchi

TrentoMember since June 29, 2026

Key Strengths

Demonstrated interest in FPGA development through projects like 'ALD_Project', 'Memory_GameVHDL', and 'LogicDesignExercises' utilizing VHDL and Verilog.
Experience with hardware description languages (VHDL, Verilog) is directly relevant to the FPGA Developer role.
Exposure to embedded systems development ('Smart-Charger-MSP432') indicates a foundational understanding of hardware-software interaction.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong inclination towards hardware-related and embedded systems development, which aligns well with an FPGA Developer role. The diversity of projects, including Rust, Python, and C++, suggests adaptability and a willingness to explore different technologies. However, the lack of professional experience or team-based projects makes it difficult to assess collaboration or broader cultural fit.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

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Projects

Smart-Charger-MSP432

March 17, 2026 – Present

Project of the course "Embedded Software for the Internet of Things"

View Project

NGN-SDN_firewall

November 17, 2025 – Present

Project for the "Next generation networks" course

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ALD_Project

September 21, 2025 – Present

ALD_Project — GitHub repository

View Project

studio12

September 11, 2025 – September 11, 2025

studio12 — GitHub repository

View Project

giorebecchi

June 15, 2025 – Present

Github profile README

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Memory_GameVHDL

April 27, 2025 – May 22, 2025

Memory_GameVHDL — GitHub repository

View Project

LogicDesignExercises

March 13, 2025 – March 14, 2025

LogicDesignExercises — GitHub repository

View Project

RollingDrone

December 11, 2024 – February 9, 2025

RollingDrone — GitHub repository

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Rolling_Drones

October 1, 2024 – July 13, 2025

Rolling_Drones — GitHub repository

View Project

Key Strengths

Demonstrated interest in FPGA development through projects like 'ALD_Project', 'Memory_GameVHDL', and 'LogicDesignExercises' utilizing VHDL and Verilog.
Experience with hardware description languages (VHDL, Verilog) is directly relevant to the FPGA Developer role.
Exposure to embedded systems development ('Smart-Charger-MSP432') indicates a foundational understanding of hardware-software interaction.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

Giovanni Rebecchi

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit