Gilad Abo

Physical Design Engineer

https://talent.gravityer.com/gilad-abo

Physical designer at Google Israel Ltd.

Google

Israel

Key Strengths

Extensive experience (16 years) in Physical Design Engineering, directly aligning with the target role.
Proven expertise in full backend design flow from synthesis to GDS, including timing and DRC fixes using industry-standard tools (Synopsys, Cadence ICC, Innovus, PrimeTime, Genus, DC).
Demonstrated leadership experience as a Backend lead for large ASIC projects with a team of approximately 30 engineers.
Experience in full chip integration, backend, and design tasks.
Prior experience in RFIC design at the transistor level, developing components like High Power Amplifiers and Low Noise Amplifiers, indicating a strong foundational understanding of analog/mixed-signal aspects relevant to physical design.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's long tenure at Marvell Israel Ltd. (over 13 years) suggests loyalty and stability. Experience across different companies (ELTA, Marvell, Google) and roles (RFIC designer, Backend engineer, Physical Design Engineer) indicates adaptability and a broad understanding of the semiconductor industry. The leadership role in a large team suggests a collaborative and influential work style. The move to Google (though future-dated in the resume) implies ambition and a desire for new challenges, which could align well with a dynamic environment.

Soft Skills & Operational Fit

The candidate's experience as a team leader for a large ASIC project suggests strong leadership, project management, and team collaboration skills. The detailed description of backend design flow indicates a methodical and process-oriented approach. However, without specific psychometric test results, a deeper assessment of work attitude, stress handling, and logical reasoning is not possible.

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Experience

Google

Physical Design Engineer

May 1, 2025 – Present

Marvell Israel Ltd.

Backend engineer

September 1, 2011 – October 1, 2025

ELTA

RFIC designer

April 1, 2010 – April 1, 2011

Key Strengths

Extensive experience (16 years) in Physical Design Engineering, directly aligning with the target role.
Proven expertise in full backend design flow from synthesis to GDS, including timing and DRC fixes using industry-standard tools (Synopsys, Cadence ICC, Innovus, PrimeTime, Genus, DC).
Demonstrated leadership experience as a Backend lead for large ASIC projects with a team of approximately 30 engineers.
Experience in full chip integration, backend, and design tasks.
Prior experience in RFIC design at the transistor level, developing components like High Power Amplifiers and Low Noise Amplifiers, indicating a strong foundational understanding of analog/mixed-signal aspects relevant to physical design.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit