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PES University
FPGA Developer
June 19, 2026 – Present
SoC_IPs
June 15, 2025 – September 11, 2025
For all the IPs that we will write for the SoC that we are designing
View ProjectRTL-Directory
March 31, 2025 – May 22, 2025
Comprises of all the basic RTL designs coded in SystemVerilog and implemented using Basys3 FPGA board.
View Projecttt09-deveshb-8-bitMAC
November 10, 2024 – April 11, 2025
TinyTapeout 9's submission repository for the 8-bit MAC unit
View Projecttt09-deveshb-active_filter
November 8, 2024 – November 8, 2024
TinyTapeout9's Analog Submission for PESU-ECC's Universal Active Filter
View ProjectCOD-Lab
August 5, 2024 – November 16, 2024
Instructions & Assignments for COD Lab - UE22EC352A
View ProjectCultural Fit Analysis
The candidate demonstrates a strong passion for FPGA development through numerous personal projects, including contributions to open-source initiatives like TinyTapeout. This indicates a proactive, self-driven individual who is likely to be a good cultural fit for a role requiring continuous learning and hands-on engagement. The diversity of projects, from basic RTL designs to RISC-V CPUs and MAC units, shows a broad interest within the FPGA domain.
Soft Skills & Operational Fit
The candidate's project descriptions are concise but lack detail regarding challenges, solutions, and personal contributions, making it difficult to assess soft skills like problem-solving, collaboration, or communication. The operational fit is good given the direct alignment of projects with the target role.