Darren

FPGA Developer

https://talent.gravityer.com/darren

National Cheng Kung University

Key Strengths

Strong foundational knowledge in Verilog and SystemVerilog for FPGA development.
Extensive experience with CPU architecture design (5-stage pipeline, single-cycle RISC-V) and AXI bus integration.
Practical experience with hardware description languages and related tools (Tcl, Makefiles).
Demonstrated ability to work on complex hardware projects, including SSD platform development.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio shows a strong focus on FPGA development, which aligns well with the target role. However, the projects are all personal or academic, and there is no information on collaborative work environments or diverse project types beyond hardware design. This limits the assessment of cultural fit.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. The candidate's experience is primarily academic and project-based, with no completed psychometric or English tests.

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Evaluating your skill match against the job requirements…

Assessing your cultural and operational fit

Projects

Verilog-Thesis-SSD_Platform

November 10, 2025 – November 10, 2025

Thesis-SSD_Platform based on Cosmos + OpenSSD

View Project

Verilog-Training-AXI-bus

October 16, 2024 – November 7, 2024

5-stage-Pipeline-CPU with AXI bus

View Project

NMC-Hardware

August 25, 2024 – April 16, 2025

Verilog-Project-NMC for NCKU CAID Lab

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Verilog-Training-ICContest

August 22, 2024 – February 16, 2025

ICContest (Update Continuously)

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Verilog-Training-Pipeline-CPU

August 21, 2024 – January 26, 2025

Verilog-Training-5-stage-Pipeline-CPU

View Project

DarrenHuang0411

May 3, 2024 – December 17, 2024

DarrenHuang0411 — GitHub repository

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RiscV-Single-Cycle-CPU-with-CSR

January 12, 2024 – January 14, 2024

RiscV-Single-Cycle-CPU-with-CSR — GitHub repository

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NCKU_CA_2023

September 30, 2023 – December 28, 2023

Computer Architecture (Fall 2023) Homework

View Project

Key Strengths

Strong foundational knowledge in Verilog and SystemVerilog for FPGA development.
Extensive experience with CPU architecture design (5-stage pipeline, single-cycle RISC-V) and AXI bus integration.
Practical experience with hardware description languages and related tools (Tcl, Makefiles).
Demonstrated ability to work on complex hardware projects, including SSD platform development.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. The candidate's experience is primarily academic and project-based, with no completed psychometric or English tests.

Darren

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Experience

Projects

Key Strengths

Cultural & Operational Fit