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Design Engineer - Contractor at asic North
VLSI Hardware Design Professional with comprehensive background in all phases of back-end design. Recognized for effectively facilitating design, development and implementation for some of the most complicated VLSI designs in the industry. Demonstrated success in mainframe, server, super computer, microprocessor, ASIC, and SOC designs. Known as an excellent troubleshooter and problem solver. Expertise includes: - Core Timing Design: server processor cores, HSS designs, ASIC processor cores - 3rd Party Acquisition - SOC Design - Physical Design: server and ASIC designs. PDS, P&R, Clocking, DFM, RIT verification and release - Circuit and Core Design: clock design, random logic library design, array design
Syracuse University
MSEE, Electrical Engineering
January 1, 1980 – January 1, 1983
University of Notre Dame
BSEE, Electrical Engineering
January 1, 1974 – January 1, 1978
ASIC North
Back-End Design Engineer - Contractor
February 1, 2014 – Present
RTP, NC
IBM - RTP, NC
CORE TIMING
February 1, 2008 – July 1, 2013
IBM - RTP, NC
3RD PARTY ACQUISITION
June 1, 2004 – February 1, 2008
IBM - RTP, NC
SYSTEM ON CHIP DESIGN
June 1, 2001 – June 1, 2004
IBM - RTP, NC
POWERPC CIRCUIT / PHYSICAL DESIGN
July 1, 1996 – June 1, 2001
IBM - RTP, NC
SP (SUPER PARALLEL) COMPUTER DESIGN
March 1, 1994 – July 1, 1996
IBM - RTP, NC
MAINFRAME DESIGN
October 1, 1987 – February 1, 1994
IBM - RTP, NC
MICROPROCESSOR CIRCUIT / ARRAY DESIGN
September 1, 1980 – October 1, 1987
IBM - RTP, NC
ADVANCED TECHNOLOGY DEVELOPMENT - CIRCUIT DESIGN
June 1, 1978 – September 1, 1980
Cultural Fit Analysis
The candidate's long tenure at IBM across diverse roles and projects demonstrates a strong ability to adapt to different technical challenges and team structures within a large corporate environment. The experience spans multiple generations of hardware design, from mainframes to modern SoC, indicating a continuous learning mindset. While the experience is deep in ASIC/SoC, the direct mention of working on a PowerPC core for Xilinx FPGA shows some alignment with the FPGA Developer target role, suggesting a potential for cultural fit in a role requiring both deep hardware understanding and FPGA specific skills. However, the primary experience is heavily weighted towards ASIC design, which may require a transition in mindset and toolchain for a pure FPGA role.
Soft Skills & Operational Fit
The candidate's extensive career at IBM, including various lead roles and project management responsibilities, suggests strong operational fit and leadership capabilities. The descriptions of working with chip-level timing designers, supervising IP integration, and leading circuit design teams indicate strong collaboration, problem-solving, and project management skills. The numerous awards and patents also point to a proactive and high-achieving individual.