Help & Supportcareers@gravityer.com
AI is analyzing your overall score…
Identifying your key strengths…
Evaluating your skill match against the job requirements…
Assessing your cultural and operational fit
CSD_Siamese_Nets
April 7, 2021 – April 7, 2021
Incorporating Siamese Networks to accurately perform facial recognition using a limited dataset.
View ProjectRainCheck
April 7, 2021 – April 7, 2021
A smart navigation system that incorporates cutting edge weather prediction to make modern day navigation techniques more efficient for intra-city travel
View ProjectStandard_Cell_Library_Characterization
April 7, 2021 – July 6, 2021
This project aims to characterize the power and timing characteristics of custom designed standard cells using the sky130A process design kit.
View ProjectStandard_cell_sky130
March 12, 2021 – April 1, 2021
Contains lef files,spice,magic files and liberty files of 21 standard cells
View ProjectTCLbasedVSDflow_Internship2021
February 10, 2021 – February 28, 2021
The internship to develop IP/VLSI system design flow at $0 cost using opensource EDA tools are being organized by https://www.vlsisystemdesign.com/ip/ . This is very good opportunity to develop skillset by doing projects on your own and implement ideas. The project topic is "TCL based 'vsdflow' for OpenLANE/Sky130" wherein VLSI system design flow (RTL to GDSII) needs to be developed using TCL scripting on OpenLANE platform using Google's free process design kit (PDK) sky130A.
View ProjectOpenlane_Workshop_VSD
January 22, 2021 – January 30, 2021
This repository will reflect the work done in the Advanced Physical Design Flow workshop, offered by the folks at VSD. It's a 5 day workshop that aims to educate us on the intricacies of Open Source EDA tools and PDKs as used by industry leaders. Furthermore, it uses Openlane flow to help understand the flow of work when it comes to VLSI designs, starting from the RTL level to the GSDII stage, performing the synthesis, placement, floorplanning, routing and sta required to do so.
View ProjectRISC-V-CPU
August 12, 2020 – August 12, 2020
This is the design of a RISC-V based CPU Micro-Architecture using TL-Verilog
View ProjectTime-Slots-G-Maps-API-s-
July 3, 2019 – July 3, 2019
This aims to generate 2 cutsomer appropriate time slots for the pickup and dropoff of excess luggage for flight travel from origin to destination respectively. The idea is to make the time slots as per the convenience of the customer and at the same time make it feasible for the commpany to perform its pickup and dropoff.
View ProjectCultural Fit Analysis
The candidate's projects show a strong inclination towards personal learning and exploration across diverse technical areas, including VLSI design and data science. This indicates a proactive and self-driven individual. However, the breadth of projects, while showing curiosity, might suggest a lack of deep specialization in a single area relevant to the 'Data Scientist' target role. The projects are primarily personal, which is common for an experience level 0 candidate, but there's no indication of team collaboration or professional project experience.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. Psychometric test scores are 0.