Ashwin Mani

FPGA Developer

https://talent.gravityer.com/ashwin-mani

MEng ECE Student uWaterloo | ex-Morgan Stanley Consultant - Backend | Aspiring to work in Software, or FPGA and Hardware Related Roles.

Member since June 29, 2026

Key Strengths

Strong foundational knowledge in Verilog and SystemVerilog, demonstrated through multiple personal projects like 'Designing-Systolic-Array', 'Modified_AES256', and 'RISCV32I_Core'.
Experience in implementing complex digital designs, including a RISC-V ISA microarchitecture.
Familiarity with hardware description languages essential for FPGA development.
Exposure to Cadence tools through 'SysVerilog_Cadence' project, indicating practical application experience.

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's project portfolio is heavily focused on hardware description languages (Verilog, SystemVerilog) and digital design, which aligns well with an FPGA Developer role. The diversity of projects, including a RISC-V core and AES implementation, suggests a strong interest and self-driven learning in the domain. However, the lack of team-based projects or professional experience makes it difficult to fully assess cultural fit beyond technical alignment.

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

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Assessing your cultural and operational fit

Projects

Velocity-Hack2025

February 21, 2025 – February 27, 2025

Patients education project for Velocity HealthCare Hackathon

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RISCV32I_Core

June 9, 2024 – June 9, 2024

The following repository contains the uArchitecture implemented for RISC-V ISA

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Ashwin4514.github.io

March 5, 2024 – March 5, 2024

Ashwin4514.github.io — GitHub repository

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Modified_AES256

January 10, 2024 – February 1, 2025

A different approach than just using Rinjdahl's sbox values using Verilog.

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ShortestPath_OptimizationSAT

January 5, 2024 – January 27, 2024

Finding Minimum Distance to reach Two points in a Street Network and Placing Minimum Traffic Signals Across a Street Network using Vertex Cover Optimization

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SysVerilog_Cadence

January 5, 2024 – January 5, 2024

This code repository contains the code used for the SystemVerilog Certification Labs

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Designing-Systolic-Array

December 9, 2023 – January 17, 2024

The following repository houses a detailed implementation of the systolic array using Verilog and System Verilog

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Obstacle-Avoidance-Wheelchair

November 16, 2023 – January 5, 2024

The following repository contains the details of our 3rd Year UG Major Project

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HTN2023

September 16, 2023 – September 30, 2023

HTN2023 — GitHub repository

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suduko-solver

August 28, 2023 – August 28, 2023

suduko-solver — GitHub repository

View Project

Key Strengths

Strong foundational knowledge in Verilog and SystemVerilog, demonstrated through multiple personal projects like 'Designing-Systolic-Array', 'Modified_AES256', and 'RISCV32I_Core'.
Experience in implementing complex digital designs, including a RISC-V ISA microarchitecture.
Familiarity with hardware description languages essential for FPGA development.
Exposure to Cadence tools through 'SysVerilog_Cadence' project, indicating practical application experience.

Cultural & Operational Fit

Cultural Fit Analysis

Soft Skills & Operational Fit

Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.

Ashwin Mani

Key Strengths

Cultural & Operational Fit

Top Skills

Skills

Projects

Key Strengths

Cultural & Operational Fit