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VLSI Engineer with 3+ years in SystemVerilog & UVM
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Design Verification Engineer with 3 years of experience in simulation-based verification, RTL/Gate-level debugging, and protocol validation. Strong expertise in SystemVerilog, UVM methodology with proven ability to debug issues, analyze waveforms, execute regressions, and collaborate with cross-functional teams to deliver high-quality silicon.
Thapar Institute of Engineering & Technology
M.Tech · VLSI Design
August 1, 2017 – June 30, 2019
Kurukshetra University
B.Tech · Electronics & Communication Engineering
August 1, 2013 – June 30, 2017
HCL Technologies
Member Technical Staff
September 1, 2021 – August 1, 2024
Noida, Uttar Pradesh, India
3ST Technologies
Intern
September 1, 2019 – March 1, 2020
Noida, Uttar Pradesh, India
STMicroelectronics
Intern
June 1, 2018 – June 1, 2019
Greater Noida, Uttar Pradesh, India
ARM Microcontroller Verification
September 1, 2021 – August 1, 2024
Contributed to functional verification of ARM-based microcontroller subsystems ensuring design correctness and robustness. - Verified key peripherals including RTC, UART, and Timer modules. - Executed regression testing and gate-level simulations (GLS). - Debugged RTL issues through detailed waveform analysis. - Updated and enhanced testcases based on RTL design changes. - Collaborated with design teams to resolve functional bugs efficiently
USB PHY / Protocol Verification
September 1, 2021 – August 1, 2024
Worked on verification of USB protocol phases and PHY-level behavior to ensure compliance with USB 2.0 specifications and reliable high-speed data communication. - Debugged USB protocol flows including Token, Data, and Handshake packets. - Analyzed SETUP → DATA → STATUS transaction phases using waveform and logs. - Validated Bulk, Control, and Interrupt transfers. - Identified and resolved issues in endpoint behavior and handshake responses. - Performed regression debugging and failure analysis to improve protocol reliability.
Cultural Fit Analysis
The candidate's experience with two different clients (Valens Semiconductor and STMicroelectronics) through HCL Technologies indicates adaptability and exposure to diverse project environments. The internship at STMicroelectronics further reinforces experience with a major semiconductor company. The projects involve core VLSI verification tasks, aligning well with the target role. The breadth of skills covers various aspects of verification, suggesting a well-rounded profile for a VLSI Engineer.
Soft Skills & Operational Fit
The candidate demonstrates an ability to collaborate with design teams to resolve functional bugs efficiently, indicating good teamwork and problem-solving skills. Experience in regression debugging and failure analysis suggests a methodical approach to verification. The professional summary highlights a 'proven ability to debug issues, analyze waveforms, execute regressions, and collaborate with cross-functional teams to deliver high-quality silicon,' which aligns well with operational requirements for a senior VLSI Engineer.