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High level synthesis, synthesis for ASIC and FPGA, Compilers for HW accelerators
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A researcher with research experience in High level synthesis Design Space Exploration and hardware design translation methodologies, currently researching on problems in kernel and SoC security, secure crypto implementations, High level synthesis security
The Hong Kong Polytechnic University
Doctor of Philosophy (Ph.D.), Computer Engineering
January 1, 2013 – January 1, 2018
Nanyang Technological University Singapore
Master of Science (MSc), Embedded Systems
January 1, 2011 – January 1, 2013
SRM University, India
Bachelor of Technology (BTech), electronics and Instrumentation
January 1, 2007 – January 1, 2011
Siemens EDA (Siemens Digital Industries Software)
Software Engineering Manager
April 1, 2026 – Present
Siemens EDA (Siemens Digital Industries Software)
Advanced Software Engineer R&D
March 1, 2023 – Present
Innatera Nanosystems
Staff Software Engineer
October 1, 2021 – March 1, 2023
Innatera Nanosystems
Senior Software Engineer
April 1, 2021 – March 1, 2023
New York University
Postdoctoral Researcher
January 1, 2020 – February 1, 2021
Brooklyn, New York
A.S. Watson Group
Senior Data Scientist
February 1, 2019 – December 1, 2019
Hong Kong
Zwoop
Machine Learning Engineer
October 1, 2017 – November 1, 2018
Hong Kong SAR
AlikeAudience
Consultant (Data Mining & Machine Learning)
October 1, 2016 – September 1, 2017
Hong Kong SAR
Hong Kong Polytechnic University
Graduate Teaching Assistant
September 1, 2013 – September 1, 2016
Hong Kong SAR
Hong Kong Polytechnic University
PhD Candidate
May 1, 2013 – August 1, 2018
Hong Kong SAR
Nanyang Technological University
Project Officer
June 1, 2012 – January 1, 2013
Singapore
Nanyang Technological University
Msc. Embedded Systems
August 1, 2011 – May 1, 2012
Singapore
SRM Nano Satellite
System Integrator,SRMSAT
January 1, 2010 – June 1, 2011
Greater Chennai Area
SRM University
Btech( Electronics and Instrumentation)
August 1, 2007 – July 1, 2011
Greater Chennai Area
Methods for abstracting RTL based VLSI designs to maximize HLS Design Space Exploration
August 1, 2014 – Present
This project involves investigation of different methodologies for abstracting RTL descriptions to C/C++ in order to automate the design space exploration for RTL level descriptions, in a more efficient way. Currently, the RTL designs are being parsed and undergoing graph transformations in order to extract behavioral detail from the hardware design and express the behaviour in C language.
Design Space Exploration for High Level Synthesis
August 1, 2013 – March 1, 2014
This project aims to develop an automated methodology for performing design space exploration of HLS designs, to provide a range of Hardware designs based on different constraints as chosen by the user, thereby abstracting the level of VLSI design to a higher level. The main contribution performed here is a proposed improved solution for exploring design space much faster and produces similar results as that of standard heuristics used for exploration.
Synthesizable SystemC benchmark suite for high level synthesis
April 1, 2013 – August 1, 2013
This benchmark suite contains designs of different domains written in SystemC. It may be used for simulation purposes or synthesizing into hardware using any commerical High Level Synthesis Tools(HLS) available in the industry. The programs are open- source and are available for direct download from this website. I encourage all to download and use these benchmarks for EDA tool feature verification.
3D Audio
March 1, 2012 – January 1, 2013
worked on DSP processors, optimization of firmware using Code Composer Studio, efficient implementation of audio signal processing algorithms on Texas Instruments DSP Processor
SRM Nano Satellite
August 1, 2010 – May 1, 2012
SRMSAT is India's first Nano Satellite built by the undergraduate students of SRM University. It is a ~10kg satellite currently monitoring green house gases emission in India. Satellite was built in a record time of 2 years. I was involved in the design of the attitude determination algorithm, Kalman estimation algorithm, and Propagation algorithm along with the development of the overal atittude determination and control systems for the nano satellite.
Cultural Fit Analysis
The candidate has a diverse background spanning academia, EDA software development, and data science. While there are significant stints in data science roles (A.S. Watson Group, Zwoop, AlikeAudience), a substantial portion of their career, particularly more recent roles, is heavily focused on hardware synthesis, VLSI, and embedded systems. The target role is 'Data Analyst', which requires a strong alignment with data analysis, visualization, and reporting, potentially less on advanced ML model development or hardware. The project diversity is high, but the alignment with a pure 'Data Analyst' role is moderate, leaning more towards a 'Data Scientist' or 'ML Engineer' profile. The breadth of skills is impressive but not all directly align with a typical Data Analyst profile.
Soft Skills & Operational Fit
The candidate's resume indicates experience in project leadership and managing interns, suggesting organizational and team collaboration skills. Their academic background and research roles imply strong analytical and problem-solving abilities. However, without specific psychometric test results or interview data, a detailed assessment of soft skills and operational fit is limited.