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MITACS GRI'21 @ UViC. GSoC'20 @Fossi . ECE Undergrad at IIITH
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PCIE-Transaction-Layer-Verification
March 26, 2024 – March 26, 2024
PCIe System Verilog Verification Environment developed for PCIe course
View ProjectIntro_To_Verilog
December 1, 2020 – December 9, 2020
Intro_To_Verilog — GitHub repository
View Projectastronomy-club-website
May 17, 2020 – June 17, 2020
Codebase for the IIIT-H astronomy club website
View Projectverilog_integration
March 10, 2020 – March 9, 2020
verilog_integration — GitHub repository
View ProjectVerilog-Example-Codes
October 1, 2019 – November 30, 2019
This is a list with various combinational and sequential circuits written in Verilog.
View ProjectCultural Fit Analysis
The candidate's projects show a diverse set of interests, ranging from hardware verification to web development and some data-related tasks. While the target role is 'Data Scientist', a significant portion of the projects are in hardware description languages, indicating a broad technical curiosity. This diversity could be a cultural fit for roles requiring adaptability, but direct alignment with a Data Scientist role is limited based on project focus.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. The candidate's project descriptions are brief, and there are no psychometric or English test scores available.