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California State University Northridge
FPGA Developer
June 28, 2026 – Present
PetaLinux_FPGA_ECE_524_Final_Proj
May 6, 2023 – May 6, 2023
Petalinux running on FPGA-z710 using ArmCortex-A9 and with YotcoProject and NGINX
View ProjectFPGA_MEMORY
March 29, 2023 – March 29, 2023
FPGA Memory Techniques utilizing BRAMS, ROM, FIFO, SRAM, DRAM
View ProjectBatch-Processing-Scheduling
March 12, 2023 – March 16, 2023
To calculate the timing parameters of batch processes based on different scheduling algorithms.
View ProjectSwitch_Debounce
February 22, 2023 – March 16, 2023
Switch bounce can result in failures, inaccurate readings, or erroneous triggering of digital logic gates in digital circuits. This effect is removed with a switch debouncer circuit, which filters the switch output signal to create a clear and steady logic signal.
View ProjectProcess-Hierarchy
February 19, 2023 – February 19, 2023
To simulate process creation and destruction when implemented with linked lists.
View ProjectColor_Detection
February 14, 2023 – February 20, 2023
Displays the color being detected by the Pmod COLOR on the monitor. The objective of this project is to implement a system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) to determine whether the data being captured by the COLOR Pmod is correct.
View ProjectCultural Fit Analysis
The candidate's projects are primarily personal and align well with the target role of FPGA Developer, indicating a strong interest and self-driven learning in the field. However, the lack of team-based projects or professional experience makes it difficult to assess collaboration and broader cultural fit. The diversity of projects is good within the FPGA domain, but limited outside of it.
Soft Skills & Operational Fit
Insufficient data to assess soft skills and operational fit. The candidate's experience level is listed as 0, and there are no completed psychometric or English tests.