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Vellore Institute of Technology, Chennai
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1-3-ROUTER
February 23, 2023 – March 19, 2023
Designed the 1:3 router that forwards data packets between computer networks using Verilog HDL and validated in Quartus Prime and Model-Sim. It drives an incoming packet to output channel based on the address field contained in the packet.
View ProjectDesign-and-Implementation-of-MAC-unit-for-Neural-Network-Applications
February 22, 2023 – March 7, 2023
Built CNN using three MAC units in Verilog and it's delay and area parameters Compared using Xilinx ISE and simulated using ModelSim
View ProjectCultural Fit Analysis
The candidate's project portfolio shows a mix of hardware description (Verilog) and early-stage machine learning projects. While there's an interest in ML, the depth and breadth of projects directly aligning with a 'Data Scientist' role are limited. The focus on Verilog suggests a background more aligned with hardware or embedded systems than pure data science. This indicates a potential mismatch with the target role's typical requirements for statistical modeling, advanced ML algorithms, and data manipulation at scale.
Soft Skills & Operational Fit
Insufficient data to assess soft skills or operational fit. No psychometric test results or interview feedback provided.