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Software Eng Manager at Apple (hiring for SDETs in SCV and San Diego)
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USC | MS in EE | FightON!
University of Southern California
Master of Science (M.S.), Electrical and Electronics Engineering
January 1, 2016 – January 1, 2018
M.S. Ramaiah Institute Of Technology
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
January 1, 2012 – January 1, 2016
Apple
Software Engineering Manager
October 1, 2023 – Present
Apple
Software Development Engineer
June 1, 2018 – October 1, 2023
Pluto7
AI ML Training Intern
January 1, 2018 – May 1, 2018
San Jose
Viterbi IT - University of Southern California Viterbi School of Engineering
Student Technical Assistant
January 1, 2017 – December 1, 2017
Greater Los Angeles Area
Information Sciences Institute
Student Researcher
January 1, 2017 – July 1, 2017
Marina Del Rey
Weenix - Unix Kernel based Operating System
October 1, 2017 – December 1, 2017
• Built the basic blocks of an UNIX kernel based operating system named "Weenix" using C. • Implemented the features of Threads, Processes, Scheduling, Context Switching and Synchronization Primitives. • In addition, implemented Virtual File System to support file abstraction APIs and Virtual memory for managing user address space, running user-level code, servicing system calls.
5-Stage and 7 Stage In-order Linear Pipeline
August 1, 2017 – September 1, 2017
• Devised, in Verilog, the RTL design of 5-stage and 7-stage in-order linear pipeline for a subset of MIPS ISA. Hazard Detection Unit and Forwarding Unit were designed to solve dependencies. Both early and late branch designs were employed in the 5-stage and 7-stage implementations. • Simulated and Tested using ModelSim 10.2v by implementation in behavioral RTL as well as structural styles using Verilog.
PageRank Computation
June 1, 2017 – July 1, 2017
• Computed PageRank for Twitter dataset using the Amazon Elastic MapReduce web service, which uses Hadoop framework to distribute and process data across a cluster of EC2 instances. Ganglia was used to monitor the high-performance systems.
IoT Security Router Network - Verilog, FPGA
February 1, 2017 – May 1, 2017
• Built a security network for wearable devices with Content Based Router • Designed a Dual Core - 4 threaded RISC-V CPU and perform it on FPGA, to processing packets content • Designed a HW accelerator to manipulate several packets decryption, encryption and rerouting based on one or up to 20 known patterns (7-byte string), the pattern could be changed.
Design and simulating 32 bit ALU using Xilinx ISE Design Suite
January 1, 2017 – Present
• Build and simulated components of ALU from scratch having five functionalities such as adder, subtraction, shifter, bitwise-AND and bitwise-OR using both methods of schematic simulation and Verilog coding. • Through the mapping process of the tools, the gate counts such as the number of D-FF and LUTs were retrieved for both the methods and the number of the gates are compared.
Measuring Bandwidth and Throughput on DETER testbed using iperf tool
January 1, 2017 – Present
• Created experiments in DETER with two computers connected with a 1Mbit/s link with about 25ms round-trip delay and the other with two computers connected with a gigabit-LAN. • Used iperf in UDP mode to measure the maximum bandwidth across the link and in TCP mode to measure the TCP throughput. • Project also involved modifying traffic shaping of a link to be set to 10 and 100Mbit/s and observing the throughput changes with changes in window sizes.
Mini-Intrusion Detection Engine Design
January 1, 2017 – Present
• Collaborated with a team of three engineers on an intrusion detection system project, that inspects packets coming from the network for a predefined signature or string using schematics, IP cores and Verilog in Xilinx ISE. • Extended this module on a programed NetFPGA reference router to count pattern matches on a per-packet basis, or to drop packets that contain a matching pattern. • Implement the H3 hash algorithm and Bloom filter in hardware to carry out fast matching of 20 different patterns
Socket Programming on DETER lab
January 1, 2017 – Present
• The client-server model is used by most inter-process communications where the client, connects to the other process like the server to make a request for information. • The system calls for establishing a connection are somewhat different for the client and the server, but both involve the basic construct of a socket which is one end of an inter-process communication channel. • Created 2 DETER nodes which run as client and server with their own socket using an enhanced code which avoids zombie problem.
Dual-core dual-threaded custom processor on NetFPGA
January 1, 2016 – February 1, 2016
• Implement a dual-core dual-threaded processor that supports a subset of RISC-V ISA on NetFPGA. • Compile the programs into RISC-V ISA and then the assembly code is translated to custom ISA using Perl scripting. • Execute a bubble sort program to completion on this custom processor to test it functionality.
Posture Monitoring and Fall Detection System for Elderly People
August 1, 2015 – June 1, 2016
Fall detection and posture monitoring is a major challenge in the healthcare domain for the elderly and requires timely and reliable surveillance. Our objective is to develop a wearable device to alert elderly people of poor posture and send alerts to caretakers if an accidental fall occurs. It consists of a microcontroller, 2 integrated sensor modules, vibrator for indicating poor posture and GPS-GSM module to send alert message to the caretaker with the person’s location. This is implemented by using a threshold based algorithm which reduces both false positives and false negatives, and has low computational cost and real-time response.
Presentations that Resonate
Duarte, Inc.
June 24, 2026 – Present
Foundations of Project Management
June 24, 2026 – Present
Google Cloud Platform Big Data and Machine Learning Fundamentals
Coursera
June 24, 2026 – Present
Cultural Fit Analysis
The candidate's project portfolio is heavily skewed towards hardware, embedded systems, and computer architecture, which is a significant mismatch for a Data Analyst role. While there is an internship with data analysis experience, the overall project diversity and career trajectory (Software Engineering Manager at Apple) do not strongly align with the typical profile of a Data Analyst. The certifications in 'Google Cloud Platform Big Data and Machine Learning Fundamentals' and 'Foundations of Project Management' show an interest in data and project management, but these are not deeply integrated into their primary experience.
Soft Skills & Operational Fit
The candidate's project descriptions indicate a strong foundation in complex problem-solving and system-level thinking. The 'Posture Monitoring' project shows an ability to develop practical solutions with real-world impact. The 'Mini-Intrusion Detection Engine Design' project highlights teamwork and collaborative engineering. However, the resume lacks explicit details on communication skills, leadership in non-management roles, or direct operational experience relevant to a Data Analyst role beyond the internship.