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Digital Design & Verification Engineer
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Assessing your cultural and operational fit
Ahmed Aly is a mid-level Digital Design and Verification Engineer with 1.3 years of experience in AI-accelerated embedded SoC development. He has expertise in functional verification, digital design, and utilizing tools like SystemVerilog and UVM. His work includes QSPI interface verification, Bluetooth Low Energy IP design, and FPGA-based TinyML accelerator research for speech recognition.
The American University in Cairo
B.Sc. · Electronics and Communications Engineering
N/A – June 30, 2026
EMASS/CND
Digital Design & Verification Engineer
June 1, 2025 – Present
Cairo, Cairo Governorate, Egypt
Huawei
Wireless & Microwave Trainee
July 1, 2024 – October 1, 2024
Cairo, Cairo Governorate, Egypt
The American University in Cairo
Academics Coordinator, Electronics Association (ECEA)
July 1, 2024 – Present
Cairo, Cairo Governorate, Egypt
KA Racing Team, Karlsruhe Institute of Technology
Suspension Team Engineer
January 1, 2020 – January 1, 2022
Karlsruhe, Baden-Württemberg, Germany
FPGA-Based TinyML Accelerator for Speech & Voice Recognition
September 1, 2025 – Present
Designing an FPGA-based hardware accelerator for CNN-based speech and voice recognition targeting resource-constrained embedded systems. Mapping neural network operations to FPGA LUTs, DSPs, and on-chip memory with focus on latency, memory footprint, and power efficiency in alignment with TinyML principles. Integrating hardware blocks via AXI interfaces and evaluating system-level performance trade-offs for real-time deployment.
Bluetooth Low Energy (BLE 6.0) Digital Design (SoC)
September 1, 2025 – Present
Contributing to BLE 6.0 IP digital design; implementing Link Layer FSM behavior, packet handling, timing coordination, and low-power design considerations.
QSPI Interface Verification (SoC)
July 1, 2025 – Present
Verified a Quad-SPI interface for an embedded SoC, ensuring protocol correctness, timing compliance, and data integrity using SystemVerilog testbenches and QuestaSim.
ALSU–Shift Register Verification - Active & Passive UVM
June 1, 2025 – Present
Verified an integrated ALSU and Shift Register system using active UVM agents for stimulus generation and passive agents for monitoring and coverage collection; ensured correctness via end-to-end scoreboard comparison.
FIFO Verification – UVM & SystemVerilog
June 1, 2025 – Present
Built a full UVM verification environment (drivers, monitors, sequences, scoreboards) with constrained-random stimulus and functional coverage to validate data ordering, flag behavior, and boundary conditions.
DSP48A1 Architecture – Verilog
June 1, 2025 – Present
Designed the DSP48A1 architecture in Verilog, created directed testbenches, and completed elaboration, synthesis, and implementation in Xilinx Vivado.
Arithmetic Logic and Shift Unit - Verilog
June 1, 2025 – Present
Designed and implemented an ALSU in Verilog supporting arithmetic, logical, and shift operations; developed directed and exhaustive testbenches and completed synthesis in Xilinx Vivado with timing closure.
SPI Slave with Single-Port RAM – Verilog
June 1, 2025 – Present
Designed an SPI slave module with integrated single-port RAM; verified memory read/write operations and SPI protocol compliance using QuestaSim; completed synthesis in Xilinx Vivado.
4-bit ALU – VLSI Full-Custom Design (65 nm)
April 1, 2025 – Present
Designed and implemented a 4-bit ALU using 65 nm CMOS technology in Cadence Virtuoso, integrating adders, shifters, comparators, and logic units at the schematic level with SPLVT NMOS/PMOS transistors.
Cultural Fit Analysis
The candidate's academic background and diverse project experience, including a racing team and an electronics association, suggest a proactive and collaborative individual. Their current role at EMASS/CND involves working in a multidisciplinary SoC team (AI, RF, digital, verification), indicating an ability to integrate into diverse technical environments. The range of academic projects, from VLSI full-custom design to FPGA-based TinyML, shows a broad technical curiosity and adaptability, which are positive indicators for cultural fit in an innovative AI engineering team.
Soft Skills & Operational Fit
The candidate demonstrates strong organizational skills through their role as Academics Coordinator, arranging workshops and establishing institutional connections. Their participation in the KA Racing Team also suggests teamwork and problem-solving abilities in a practical engineering context. The detailed project descriptions indicate a methodical approach to design and verification, which is beneficial for operational fit.