Aashish Pandey

FPGA Developer

https://talent.gravityer.com/aashish-pandey-1

Computer Engineer

Member since June 29, 2026

Key Strengths

Extensive experience in SystemVerilog for IP core development and verification.
Proficiency in UVM methodology for complex verification environments.
Strong background in formal verification using SVA and JasperGold.
Experience with Python for automation in verification flows.
Demonstrated ability to work on production-grade IP cores (I2C-IP).

Cultural & Operational Fit

Cultural Fit Analysis

The candidate's projects show a strong focus on hardware description languages and verification, which aligns well with an FPGA Developer role. However, the project diversity outside of this core area is limited, with several basic web development projects that do not directly contribute to the target role's cultural fit. The candidate's experience level is listed as 0, which contradicts the depth of their personal projects, suggesting a potential mismatch in self-assessment or a very early career stage with advanced personal learning.

Soft Skills & Operational Fit

Insufficient data to assess soft skills and operational fit. No psychometric test results or interview feedback provided.

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Projects

opentitan-i2c-dv

March 28, 2026 – Present

UVM verification environment for the OpenTitan I2C IP — constrained-random testbench, functional coverage, and SVA properties targeting the official OpenTitan testplan.

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curve-fitting

March 18, 2026 – Present

This is a curve fitting function, which fits the curve using standard python functions only and not the scipy or other libraries

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I2C-IP

March 16, 2026 – Present

A production-grade I2C IP core written in SystemVerilog with a complete UVM 1.2 verification environment, SVA assertion suite, JasperGold formal properties, and Python-based automation.

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lsu_uvm_verification

February 10, 2026 – Present

A layered SystemVerilog UVM verification environment for a Load Store Unit (LSU) DUT, implementing reusable agent, environment, sequence, and test components to demonstrate scalable functional verification methodology.

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Design_Automation

February 8, 2026 – Present

Design_Automation — GitHub repository

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llm-fveval

December 28, 2025 – Present

Implementation of an FVEval-style framework for evaluating the formal usefulness of SystemVerilog assertions.

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GaneshChaturthiSpecial

August 31, 2022 – August 31, 2022

GaneshChaturthiSpecial — GitHub repository